Electrical interconnect bridge

ABSTRACT

Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

TECHNICAL FIELD

Embodiments described herein relate generally to electronic devicepackages, and more particularly to interconnect bridges of packagesubstrates.

BACKGROUND

High bandwidth interconnects on a package are becoming increasinglyimportant for high performance computing. The embedded multi-dieinterconnect bridge (EMIB), pioneered and developed by Intel®, is abreakthrough that addresses this need and facilitates a lower cost andsimpler 2.5D packaging approach for very high density interconnectsbetween heterogeneous dies on a single package. Instead of an expensivesilicon interposer with “through silicon vias” (TSV), a typical EMIBcomprises a small silicon bridge chip that is embedded in the packagesubstrate, enabling very high density die-to-die connections only whereneeded, such as with fine line and spaced (FLS) traces. Standardflip-chip assembly is used for robust power delivery and to connecthigh-speed signals directly from a chip to a package substrate. The EMIBeliminates the need for TSVs and specialized interposer silicon that addcomplexity and cost.

BRIEF DESCRIPTION OF THE DRAWINGS

Invention features and advantages will be apparent from the detaileddescription which follows, taken in conjunction with the accompanyingdrawings, which together illustrate, by way of example, variousinvention embodiments; and, wherein:

FIG. 1 illustrates a schematic cross-section of an electronic devicepackage in accordance with an example;

FIG. 2 illustrates a schematic cross-section of an electricalinterconnect bridge in accordance with an example;

FIG. 3 illustrates trace, via, and via pad dimensions in accordance withan example;

FIG. 4A illustrates patterning conductive elements of an interconnectbridge using a dry film resist (DFR) lamination in accordance with anexample of a method for making an electrical interconnect bridge;

FIG. 4B illustrates building up conductive elements of an interconnectbridge in accordance with an example of a method for making anelectrical interconnect bridge;

FIG. 4C illustrates removing DFR lamination in accordance with anexample of a method for making an electrical interconnect bridge;

FIG. 4D illustrates forming a spacer on a conductive element inaccordance with an example of a method for making an electricalinterconnect bridge;

FIG. 4E illustrates disposing a material at least partially aboutlateral sides of a spacer in accordance with an example of a method formaking an electrical interconnect bridge;

FIG. 4F illustrates removing a spacer to form an opening in the materialin communication with the conductive element in accordance with anexample of a method for making an electrical interconnect bridge;

FIG. 4G illustrates disposing conductive material in the opening to forma via in accordance with an example of a method for making an electricalinterconnect bridge;

FIG. 4H illustrates patterning conductive elements on a routing layer ofan interconnect bridge using DFR lamination in accordance with anexample of a method for making an electrical interconnect bridge;

FIG. 4I illustrates building up conductive elements on a routing layerof an interconnect bridge in accordance with an example of a method formaking an electrical interconnect bridge;

FIG. 4J illustrates removing DFR lamination from a routing layer inaccordance with an example of a method for making an electricalinterconnect bridge;

FIG. 4K illustrates removing excess conductive material from a routinglayer in accordance with an example of a method for making an electricalinterconnect bridge;

FIG. 5 illustrates compression molding material about a spacer inaccordance with an example of a method for making an electricalinterconnect bridge;

FIG. 6 illustrates an electrical interconnect bridge with multiplerouting layers of conductive elements coupled by vias disposed on acarrier in accordance with an example of a method for making anelectrical interconnect bridge;

FIG. 7 illustrates removal of the carrier to form an electricalinterconnect bridge in accordance with an example of a method for makingan electrical interconnect bridge;

FIG. 8A illustrates a plurality of electrical interconnect bridgesdisposed on a carrier in accordance with an example of a method formaking an electrical interconnect bridge;

FIG. 8B illustrates disposed encapsulant material over a plurality ofelectrical interconnect bridges in accordance with an example of amethod for making an electrical interconnect bridge;

FIG. 8C illustrates singulating and removing a plurality of electricalinterconnect bridges having encapsulant material from a carrier inaccordance with an example of a method for making an electricalinterconnect bridge; and

FIG. 9 is a schematic illustration of an exemplary computing system.

Reference will now be made to the exemplary embodiments illustrated, andspecific language will be used herein to describe the same. It willnevertheless be understood that no limitation of the scope or tospecific invention embodiments is thereby intended.

DESCRIPTION OF EMBODIMENTS

Before invention embodiments are disclosed and described, it is to beunderstood that no limitation to the particular structures, processsteps, or materials disclosed herein is intended, but also includesequivalents thereof as would be recognized by those ordinarily skilledin the relevant arts. It should also be understood that terminologyemployed herein is used for the purpose of describing particularexamples only and is not intended to be limiting. The same referencenumerals in different drawings represent the same element. Numbersprovided in flow charts and processes are provided for clarity inillustrating steps and operations and do not necessarily indicate aparticular order or sequence. Unless defined otherwise, all technicaland scientific terms used herein have the same meaning as commonlyunderstood by one of ordinary skill in the art to which this disclosurebelongs.

As used in this written description, the singular forms “a,” “an” and“the” provide express support for plural referents unless the contextclearly dictates otherwise. Thus, for example, reference to “a layer”includes a plurality of such layers.

In this application, “comprises,” “comprising,” “containing” and“having” and the like can have the meaning ascribed to them in U.S.Patent law and can mean “includes,” “including,” and the like, and aregenerally interpreted to be open ended terms. The terms “consisting of”or “consists of” are closed terms, and include only the components,structures, steps, or the like specifically listed in conjunction withsuch terms, as well as that which is in accordance with U.S. Patent law.“Consisting essentially of” or “consists essentially of” have themeaning generally ascribed to them by U.S. Patent law. In particular,such terms are generally closed terms, with the exception of allowinginclusion of additional items, materials, components, steps, orelements, that do not materially affect the basic and novelcharacteristics or function of the item(s) used in connection therewith.For example, trace elements present in a composition, but not affectingthe composition's nature or characteristics would be permissible ifpresent under the “consisting essentially of” language, even though notexpressly recited in a list of items following such terminology. Whenusing an open ended term in the written description like “comprising” or“including,” it is understood that direct support should be affordedalso to “consisting essentially of” language as well as “consisting of”language as if stated explicitly and vice versa.

The terms “first,” “second,” “third,” “fourth,” and the like in thedescription and in the claims, if any, are used for distinguishingbetween similar elements and not necessarily for describing a particularsequential or chronological order. It is to be understood that the termsso used are interchangeable under appropriate circumstances such thatthe embodiments described herein are, for example, capable of operationin sequences other than those illustrated or otherwise described herein.Similarly, if a method is described herein as comprising a series ofsteps, the order of such steps as presented herein is not necessarilythe only order in which such steps may be performed, and certain of thestated steps may possibly be omitted and/or certain other steps notdescribed herein may possibly be added to the method.

The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,”“under,” and the like in the description and in the claims, if any, areused for descriptive purposes and not necessarily for describingpermanent relative positions. It is to be understood that the terms soused are interchangeable under appropriate circumstances such that theembodiments described herein are, for example, capable of operation inother orientations than those illustrated or otherwise described herein.The term “coupled,” as used herein, is defined as directly or indirectlyconnected in an electrical or nonelectrical manner. Objects describedherein as being “adjacent to” each other may be in physical contact witheach other, in close proximity to each other, or in the same generalregion or area as each other, as appropriate for the context in whichthe phrase is used. Occurrences of the phrase “in one embodiment,” or“in one aspect,” herein do not necessarily all refer to the sameembodiment or aspect.

As used herein, the term “substantially” refers to the complete ornearly complete extent or degree of an action, characteristic, property,state, structure, item, or result. For example, an object that is“substantially” enclosed would mean that the object is either completelyenclosed or nearly completely enclosed. The exact allowable degree ofdeviation from absolute completeness may in some cases depend on thespecific context. However, generally speaking the nearness of completionwill be so as to have the same overall result as if absolute and totalcompletion were obtained. The use of “substantially” is equallyapplicable when used in a negative connotation to refer to the completeor near complete lack of an action, characteristic, property, state,structure, item, or result. For example, a composition that is“substantially free of” particles would either completely lackparticles, or so nearly completely lack particles that the effect wouldbe the same as if it completely lacked particles. In other words, acomposition that is “substantially free of” an ingredient or element maystill actually contain such item as long as there is no measurableeffect thereof.

As used herein, the term “about” is used to provide flexibility to anumerical range endpoint by providing that a given value may be “alittle above” or “a little below” the endpoint.

As used herein, a plurality of items, structural elements, compositionalelements, and/or materials may be presented in a common list forconvenience. However, these lists should be construed as though eachmember of the list is individually identified as a separate and uniquemember. Thus, no individual member of such list should be construed as ade facto equivalent of any other member of the same list solely based ontheir presentation in a common group without indications to thecontrary.

Concentrations, amounts, sizes, and other numerical data may beexpressed or presented herein in a range format. It is to be understoodthat such a range format is used merely for convenience and brevity andthus should be interpreted flexibly to include not only the numericalvalues explicitly recited as the limits of the range, but also toinclude all the individual numerical values or sub-ranges encompassedwithin that range as if each numerical value and sub-range is explicitlyrecited. As an illustration, a numerical range of “about 1 to about 5”should be interpreted to include not only the explicitly recited valuesof about 1 to about 5, but also include individual values and sub-rangeswithin the indicated range. Thus, included in this numerical range areindividual values such as 2, 3, and 4 and sub-ranges such as from 1-3,from 2-4, and from 3-5, etc., as well as 1, 2, 3, 4, and 5,individually.

This same principle applies to ranges reciting only one numerical valueas a minimum or a maximum. Furthermore, such an interpretation shouldapply regardless of the breadth of the range or the characteristicsbeing described.

Reference throughout this specification to “an example” means that aparticular feature, structure, or characteristic described in connectionwith the example is included in at least one embodiment. Thus,appearances of the phrases “in an example” in various places throughoutthis specification are not necessarily all referring to the sameembodiment.

Furthermore, the described features, structures, or characteristics maybe combined in any suitable manner in one or more embodiments. In thisdescription, numerous specific details are provided, such as examples oflayouts, distances, network examples, etc. One skilled in the relevantart will recognize, however, that many variations are possible withoutone or more of the specific details, or with other methods, components,layouts, measurements, etc. In other instances, well-known structures,materials, or operations are not shown or described in detail but areconsidered well within the scope of the disclosure.

Example Embodiments

An initial overview of technology embodiments is provided below andspecific technology embodiments are then described in further detail.This initial summary is intended to aid readers in understanding thetechnology more quickly but is not intended to identify key or essentialfeatures of the technology nor is it intended to limit the scope of theclaimed subject matter.

Although a typical EMIB offers significant advantages and cost benefitsover other solutions available for die interconnects such as siliconinterposer or high density substrate surface layers, a typical EMIB doeshave some drawbacks. For example, a typical EMIB bridge is constructedof silicon and manufactured with costly wafer fabrication processes.Also, the silicon material has a low coefficient of thermal expansion(CTE) compared to the build-up dielectric material of package substratesin which the silicon is embedded. As a result, a typical EMIB suffersfrom thermomechanical issues such as stresses, warpage, etc. due to thedifferential thermal expansion of the materials involved.

Accordingly, electrical interconnect bridges are disclosed which areformed of low-cost material that can be constructed utilizing low-costtechniques while providing FLS traces on multiple routing layers. In oneaspect, thermomechanical issues can be mitigated to a certain extent bythe electrical interconnect bridges of the present disclosure. In oneexample, an electrical interconnect bridge in accordance with thepresent disclosure can include a bridge substrate formed of a moldcompound material. The electrical interconnect bridge can also include aplurality of routing layers within the bridge substrate, each routinglayer having a plurality of FLS traces. In addition, the electricalinterconnect bridge can include a via extending through the substrateand electrically coupling at least one of the FLS traces in one of therouting layers to at least one of the FLS traces in another of therouting layers.

Referring to FIG. 1, an exemplary electronic device package 100 isschematically illustrated in cross-section. The package 100 can includea package substrate 110 and a plurality of electronic components 120,121 mounted on or otherwise coupled to the package substrate 110. Thepackage 100 can also include an electrical interconnect bridge 130embedded in the package substrate 110 to electrically couple the firstelectronic component 120 and the second electronic component 121, forexample, to route electrical signals between the electronic components120, 121. The bridge 130 may generally be identified as an example of anembedded multi-die interconnect bridge (EMIB) architecture or assembly.The bridge 130 embedded in the package substrate 110 can form anelectronic device package substrate assembly 101.

The electronic components 120, 121 can be any electronic device orcomponent that may be included in an electronic device package, such asa semiconductor device (e.g., a die, a chip, or a processor). In oneembodiment, each of the electronic components 120, 121 may represent adiscrete chip. The electronic components 120, 121 may be, include, or bea part of a processor, memory, or application specific integratedcircuit (ASIC) in some embodiments. The electronic components 120, 121can be attached to the package substrate 110 according to a variety ofsuitable configurations including, a flip-chip configuration, asdepicted, or other configurations such as wire bonding and the like. Inthe flip-chip configuration, active sides of the electronic components120, 121 are attached to a surface of the package substrate 110 usinginterconnect structures 122 such as bumps or pillars, as shown. Theinterconnect structures 122 may be configured to route electricalsignals between the electronic components 120, 121 and the packagesubstrate 110. In some embodiments, the interconnect structures 122 maybe configured to route electrical signals such as, for example, I/Osignals and/or power or ground signals associated with the operation ofthe electronic components 120, 121.

The package substrate 110 may include electrical routing featuresconfigured to route electrical signals to or from the electroniccomponents 120, 121. The electrical routing features may be internaland/or external to the bridge 130. For example, in some embodiments, thepackage substrate 110 may include electrical routing features such aspads or traces configured to receive the interconnect structures 122 androute electrical signals to or from the electronic components 120, 121.Package level interconnects (not shown) such as, for example, solderballs, may be coupled to a surface of the package substrate 110 tofurther route the electrical signals to other electrical devices (e.g.,motherboard or other chipset). In some embodiments, the packagesubstrate 110 is an epoxy-based laminate substrate having a core and/orbuild-up layers. The package substrate 110 may include other suitabletypes of substrates in other embodiments.

The bridge 130 may be a dense interconnect structure that provides aroute for electrical signals. The bridge 130 may include a bridgesubstrate 131 having electrical routing features formed thereon toprovide a chip-to-chip connection between the electronic components 120,121. The bridge 130 may be embedded in a cavity of the package substrate110 in some embodiments. The bridge 130 may comport with embodimentsdescribed in connection with other figures herein. In some embodiments,a portion of the electronic components 120, 121 may overlie the embeddedbridge 130, as illustrated.

The bridge 130 can include electrically conductive pads at leastpartially on or in a top surface of the bridge. The electricallyconductive pads can include conductive metal, such as copper, gold,silver, aluminum, zinc, nickel, brass, bronze, iron, etc. A dielectriclayer can be formed over the bridge 130 and the package substrate 110.Conductive vias and solder connections can pass through the dielectriclayer. In one aspect, such a dielectric layer can allow for dimensionalvariations in the placement of the embedded bridge 130 and canelectrically isolate interconnection areas. The dielectric layer caninclude oxide, or other materials, such as insulating materials.

The package substrate 110 may be formed of any suitable semiconductormaterial (e.g., a silicon, gallium, indium, germanium, or variations orcombinations thereof, among other substrates), one or more insulatinglayers, such as glass-reinforced epoxy, such as FR-4,polytetrafluoroethylene (Teflon), cotton-paper reinforced epoxy (CEM-3),phenolic-glass (G3), paper-phenolic (FR-1 or FR-2), polyester-glass(CEM-5), ABF (Ajinomoto Build-up Film), any other dielectric material,such as glass, or any combination thereof, such as can be used inprinted circuit boards (PCBs).

Although two electronic components 120, 121 electrically coupled by asingle bridge 130 are depicted in FIG. 1, other embodiments may includeany suitable number of electronic components and bridges connectedtogether in other possible configurations including three-dimensionalconfigurations. For example, another electronic component that isdisposed on the package substrate 110 in or out of the page relative tothe electronic components 120, 121 of FIG. 1 may be coupled to one orboth of the electronic components 120, 121 using another bridge.

FIG. 2A illustrates an electrical interconnect bridge 230 in accordancewith an example of the present disclosure. The bridge 230 can beincorporated with a package substrate as discussed above with respect toFIG. 1. The bridge 230 can include a bridge substrate 231 and multiplerouting layers 232 a-d. The bridge substrate 231 can comprise anysuitable material and be made by any suitable process. As discussed inmore detail below, the bridge substrate of one or more of the routinglayers 232 a-d can include a mold compound material. In the embodimentillustrated in FIG. 2A, the bridge substrate of multiple routing layersincludes the same material (e.g., mold compound), which therefore havethe same coefficient of thermal expansion (CTE). In one aspect, allrouting layers of the bridge substrate can comprise the same materialand CTE. The CTE of the material of the routing layers 232 a-d can befrom about 7 to about 50 ppm per degree Celsius. In some embodiments,the CTE of the material of the routing layers 232 a-d can be from about7 to about 25 ppm per degree Celsius. The material of the routing layerscan therefore have a CTE that is higher than that of silicon (about 3ppm per degree Celsius), which can mitigate thermomechanical issues tosome extent. The bridge substrate 231 can also optionally include anencapsulant material 233 disposed at least partially about each of therouting layers 232 a-d, such that the encapsulant material is proximateto a portion of a package substrate in which the bridge is embedded, asin FIG. 1. Any suitable encapsulant material can be utilized anddisposed about the bridge substrate in any suitable manner, such asmolding an over-mold material about the bridge substrate. Theencapsulant material can have any suitable CTE.

Each routing layer 232 a-d can include traces 234 a-f to electricallycouple electronic components. The bridge 230 is oriented 90 degreesrelative to the orientation of the bridge shown in FIG. 1, such thattraces extend into and out of the page in FIG. 2. One or more vias 235a-d can extend through the bridge substrate 231 and electrically coupleone or more of the traces in one routing layer to one or more of thetraces in another routing layer. Although FIG. 2 shows vias electricallycoupling traces in four routing layers, it should be recognized that thebridge substrate 231 can include any suitable number of routing layershaving any suitable number of traces, and that any suitable number ofvias can be utilized to electrically connect traces in different routinglayers. In addition, the vias can have any suitable shape orconfiguration, such as a circular and/or non-circular (e.g.,rectangular) cross-section.

FIG. 3 is a top-down example of pads, traces, and vias in accordancewith various embodiments. Specifically, FIG. 3 depicts a top-down viewof one routing layer of a bridge as disclosed herein. The bridge mayinclude a plurality of traces such as traces 334 a-c. In someembodiments, the traces 334 a-c may be copper, while in otherembodiments the traces may be some other electrically and/or thermallyconductive material.

In some embodiments, some of the traces such as traces 334 a and 334 ccan be coupled with a pad such as via pads 336 a and 336 c,respectively. The pads 336 a, 336 c can be constructed of a same orsimilar materials as the traces 334 a-c. For example, the pads 336 a,336 c may be constructed of copper. In other embodiments the pads 336 a,336 c can be constructed of a different material than the traces 334a-c, for example, some other electrically and/or thermally conductivematerial.

As shown in FIG. 3, the pads 336 a, 336 c can have a larger footprintthan the traces 334 a-c, as will be discussed below. As discussedherein, “footprint” may generally refer to the lateral size of theelement. Similarly, it can be seen that not all traces may be directlycoupled with a pad. For example, the trace 334 b may not be coupled witha pad. In some embodiments, the pads 336 a, 336 c can be coupled withone or more conductive vias such as vias 335 a and 335 c. As shown inFIG. 3, the vias 335 a, 335 c can have a smaller footprint than the pads336 a, 336 c. That is, the vias 335 a, 335 c may have a smaller diameterthan the pads 336 a, 336 c. The smaller diameter of the vias may be toprovide a small margin of error during manufacturing such that if thevia is not placed directly on the center of the pad, the via may notextend beyond the perimeter of the pad. It will be understood thatalthough the traces 334 a-c are depicted as generally linear, and thepads 336 a, 336 c and vias 335 a, 335 c are depicted as generallycircular, in other embodiments the traces, pads, and/or vias may have adifferent shape.

In one aspect, the traces 334 a-c can comprise fine line and spaced(FLS) traces, which are characterized by certain dimensional attributes.FIG. 3 illustrates a variety of measurements or dimensions referred toherein. For example, the distance between the center of the pads 336 aand 336 c is a value depicted in FIG. 3 as “X.” Similarly, the traces334 a-c have a width depicted in FIG. 3 as “Y.” The distance between twoelements, such as between the pads 336 a, 336 c and the trace 334 b, isa value depicted in FIG. 3 as “Z.” The dimension Z is generally referredto herein as the space between traces, which may be indicative of thespace between two elements, such as the space between two traces (e.g.,between traces 334 a and 334 b) or the space between a trace and a viapad (e.g., between the via pad 336 a and the trace 334 b), as applicablefor a given embodiment or configuration. A plurality of traces isreferred to herein, such as in the context of a routing layer. Such aplurality of traces includes traces and via pads, which are connected tothe traces and disposed in the same routing layer. Thus, reference to aspacing between traces in a plurality of traces includes reference tothe space between two traces and/or the space between a trace and a viapad.

Generally, the values for X, Y, and Z may be given on the order ofmicrons. The values for Y and Z may be on the order of approximately 10μm or less, respectively. Such FLS traces with a width of approximately10 μm or less and/or that are spaced approximately 10 μm or less apartfrom one another are referred to herein as 10/10 L/S. Smaller values forY and/or Z may allow the value of X to decrease. Being able to achievethese smaller values for X, Y, and/or Z may provide significantbenefits. For example, as performance demands on bridges increase, itmay be useful to provide more I/O ports. A smaller FLS may allow formore traces and/or pads to be placed in a routing layer of a bridge,thereby allowing an increased number of I/O ports without increasingcost and/or z-height.

FIGS. 4A-8C illustrate aspects of an exemplary method or process formaking an electrical interconnect bridge as disclosed herein. FIG. 4Arepresents a process for patterning conductive elements (e.g., traces)of an interconnect bridge using a dry film resist (DFR) lamination. Inthis process, a dry film laminate 440 is applied to a conductive (e.g.,copper) layer 441, which is supported by a carrier panel 442. Theconductive layer 441 may be included with the carrier panel 442 in theform of a foil or a seed layer of conductive material may be provided asneeded, such as if the foil is not sufficient. The film is exposed anddeveloped to provide a pattern for the conductive elements. The patterncan be configured to provide any suitable conductive elementconfiguration or dimension. For example, the pattern can be configuredto provide conductive elements with dimensions and spacingcharacteristic of FLS traces. Using the pattern, conductive elements 434a-c can be built up on the conductive layer 441, such as by electrolyticplating of copper on the layer, as represented in FIG. 4B. Once theconductive elements 434 a-c have been formed, the DFR laminate can beremoved or stripped away, as represented in FIG. 4C.

The carrier panel 442 may be referred to as a “peelable core”. Thiscarrier panel 442 may have different configurations in variousembodiments. In some embodiments, the carrier panel may include twocopper layers that are separated by a weak layer that may allow forseparation of a manufactured non-singulated molded bridge substrate fromthe carrier. In this case, at the end of the process described below, acopper etch process may be used to remove the sacrificial copper layer,i.e. the copper layer that remains attached to the manufacturednon-singulated molded bridge substrate subsequent to separation of thesubstrate from the carrier. However, other embodiments may include twodielectric layers, or a dielectric layer and a copper layer to allow forpeeling. In embodiments where the sacrificial material after peel is adielectric material, a removal process such as wet-blast or some otherremoval process may be used to remove this dielectric material insteadof the above-described copper etch process. Other types of carriers suchas a releasable tape and metal carrier can also be used. In such a case,a seed metal layer such as copper may be deposited before proceeding tothe subsequent process steps. Accordingly, a thermal release andsubsequent tape residue clean up step may be performed before copperetch as described in the peelable core case.

FIGS. 4D-4G illustrate aspects of a method for making a via forelectrically coupling conductive elements of a bridge as disclosedherein. FIG. 4D illustrates forming a spacer 450 on a suitableconductive element, such as the conductive element 434 b, which may beconfigured as a via pad. As further explained below, the spacer 450 is atemporary structure that provides a space or opening for the formationof a via between conductive elements of different routing layers. A viaformed in such a spacer opening will have dimensional characteristicsand geometry similar to that of the spacer 450. Thus, the spacer 450 canhave a shape that is circular or non-circular (e.g., rectangular) incross-section depending on the desired configuration of the via to beformed. The spacer 450 can also have dimensional attributes that reflectthe desired dimensional attributes of a via to be formed.

When manufacturing pads and vias, the pad to via alignment tolerancesmay require that pads are sized to be larger than the alignmenttolerances of the process to ensure that the entire via lands on thepad. As a result, the size of the pads may be limiting with regard tothe number of traces that can be routed on any given layer.Consequently, improving the alignment capability of the pad and viamanufacturing process can increase the number of traces in a routinglayer. Typically, the spacer 450 will be formed by a technique orprocess that enables the spacer to have dimensional characteristics andpositioning consistent with FLS traces so that a via formed in thespacer opening will have acceptable alignment with a trace pad. Thespacer 450 can be formed by any suitable technique or process. In oneaspect, the spacer 450 can be formed by curtain coating, spin coating,printing, dispensing, etc. to dispose material on the conductive element434 b. For example, in some embodiments, a high precision inkjet printermay be used to place the spacer 450 precisely at the desired locationusing unit level alignment, thereby resulting in a tighter via to padtolerance. This tighter tolerance may enable a smaller value of X asdescribed herein. As a result, the underlying pad size may then besignificantly reduced to enable FLS interconnects. In other embodiments,the spacer 450 can be curtain coated, photo exposed, and developed,which may result in a tight via to pad tolerance enabling FLSinterconnects. In some cases, a shape of the spacer 450 can be definedonce material has been disposed on the conductive element 434 b. In suchcases, the shape of the spacer 450 can be defined by photoexposing/defining the shape or pattern, dry etching the shape orpattern, and/or any other suitable technique or process for defining ashape or pattern in preexisting or pre-applied spacer material.

Because the spacer 450 is temporary and is subsequently removed, asdescribed below, to facilitate formation of a via, the spacer can bemade or constructed of any suitable material that may facilitate removalof the spacer. For example, the spacer 450 can be made of a sacrificialmaterial that can maintain sufficient dimensional stability tofacilitate formation of a via as described herein, and also facilitateremoval of the spacer when desired. In one aspect, the sacrificialmaterial can be thermally decomposable, although any suitable type ofsacrificial material can be utilized, such as liquid soluble materials.Examples of suitable sacrificial materials include polynorbornene and/orpolycarbonate based polymers that decompose when exposed to a relativelyhigh temperature. Such temperature may be at or above 180 degreesCelsius in some embodiments. In other embodiments, the temperature maybe at or above 200 degrees Celsius. In some embodiments, an additionalcleaning step may be necessary to remove remnants of the sacrificialelement 450 from the via 452.

In one aspect, FIG. 4D also illustrates an electrical interconnectbridge precursor, which includes a trace (e.g., conductive element 434b) having a via pad, and a spacer 450 formed of a sacrificial materialdisposed on the via pad. The electrical interconnect bridge precursorillustrated also includes a carrier panel 442 supporting the trace.

In FIG. 4E, a material 460 is disposed at least partially about lateralsides of the spacer 450. The material 460 can form a portion of a bridgesubstrate routing layer and, as such, can comprise any suitable materialfor a bridge substrate. The material 460 can be disposed about thespacer 450 by any suitable dispensing technique or process, and can beof any suitable form (e.g., a viscous form, solid particles, a sheet,etc.). Subsequently, the material 460 will be molded by any suitablemold technique (e.g., a compression molding process and/or a transfermolding process) about the spacer 450, and therefore the material 460can comprise any suitable mold material, such an epoxy mold compound.

Compression molding the material 460 about the spacer 450 can beadvantageous, as illustrated in FIG. 5. In this case, the spacer 450,which may be made of a relatively elastic or flexible material (e.g., apolymer), can be axially compressed 461 to a certain extent and moldedflush with the material 460. A mold release material 462 can be used tofacilitate release of the mold material 460 and/or the spacer 450 from amold component. In addition to axial compressive forces 461, lateralforces 463 acting on the spacer 450 from the mold material 460 canmaintain the spacer 450 in place (e.g., little to no movement) duringthe compression molding process. Thus, an exposed top portion of thespacer 450 can be flush with the top of the mold material 460 as aresult of the compression mold process, which obviates the need for anyadditional processing (e.g., grinding) to achieve such a relationship,thereby reducing cost and improving yield. In addition, since grindingof the mold compound may be not required, the surface of the moldcompound may not be inherently damaged, thereby enabling significantlyhigher reliability and ability to pattern finer lines and spaces.

In one aspect, FIG. 4E also illustrates an electrical interconnectbridge precursor, which in this case further includes material 460(e.g., mold compound) disposed at least partially about lateral sides ofthe spacer 450. The spacer 450 can be made of a sacrificial material,which can facilitate removal of the spacer such that an opening remainsin the material 460 in communication with a via pad, as discussed below.

For example, FIG. 4F illustrates the spacer removed to form an opening452 in the material 460 in communication with the conductive element 434b. The spacer can be removed by any suitable technique or process. Asmentioned above, the spacer can be made of a sacrificial material, whichcan facilitate removal of the spacer by exposure to heat and/or liquid.In one aspect, therefore, the spacer can be removed by heating thespacer to a temperature sufficient to decompose the sacrificial material(e.g., to a gas) while not negatively impacting the surroundingmaterials or structures (e.g., melting the material 460). Because thespacer is maintained in place when the material 460 is disposed aboutthe spacer (e.g., during compression molding), a tight profile for a viais established by the opening 452 that is formed in the material 460 bythe removal of the spacer, which can facilitate the formation of a viahaving minimal misalignment with the underlying pad.

With an opening formed in the material 460 by the removal of the spacer,a conductive material (e.g., copper) can be disposed in the opening 452to form a via 435, as illustrated in FIG. 4G. A conductive material canbe disposed in the opening 452 by any suitable technique or process,such as forming a seed layer of the conductive material and/or platingthe conductive material. Conductive material can also be disposed on thematerial 460 to form a thin conductive layer 441′ (e.g., a seed layerfor the formation of additional conductive elements).

Conductive elements (e.g., traces) for the next routing layer can beformed in any suitable manner, such as was previously described withreference to FIGS. 4A-4C. For example, FIG. 4H represents a process forpatterning conductive elements (e.g., traces) of an interconnect bridgeusing DFR lamination, where a dry film laminate 440′ is applied to theconductive layer 441′ formed on the material 460. The film is exposedand developed to provide a pattern for conductive elements of the nextrouting layer. The pattern can be configured to provide any suitableconductive element configuration or dimension. For example, the patterncan be configured to provide conductive elements with dimensions andspacing characteristic of FLS traces. Using the pattern, conductiveelements 434 a′-c′ can be built up on the conductive layer 441′ and thevia 435, such as by electrolytic plating of copper on the conductivelayer, as represented in FIG. 4I. This process can also fill the openingin the material 460 with conductive material, thus further forming thevia 435. Once the conductive elements 434 a′-c′ have been formed, theDFR laminate can be stripped away, as represented in FIG. 4J. Exposedportions 443 a-d of conductive material extending from and between theconductive elements 434 a′-c′ can be removed or stripped as shown inFIG. 4K to ensure no unwanted electrical coupling of the conductiveelements.

At this point, the process described in FIGS. 4D-4G can be repeated toform another via extending to another routing layer, and the processdescribed in FIGS. 4H-4K can be repeated to form conductive elements ofthe next routing layer. These processes can be repeated to form anydesired number of vias and routing layers. Because multiple DFRstripping techniques may not be necessary for each layer, the overallcost and manufacturing complexity of the package may be reduced.

When no more routing layers are desired, material (e.g., mold compound)can be formed around exposed conductive elements (e.g., conductiveelements 434 a′-c′ illustrated in FIG. 4K) to cover the conductiveelements and form the final bridge substrate routing layer. The resultof this process can be a bridge with multiple routing layers of FLStraces coupled by vias, as illustrated in FIG. 6. Desired CTE for moldcompound materials can be achieved by modifying mold formulations, suchas by lowering filler content and/or modifying the fillers. For example,the table below shows some mold compound formulations that can be usedfor the bridge substrate.

Varying CTE with Filler Content Mold CTE Type Compound Filler (ppm/° C.)Granular Epoxy Phenol Silica 7-24 Liquid Epoxy Anhydride Silica 7-24Liquid Epoxy Amine Silica 7-24 Granular Epoxy Phenol Silica 7-50Granular Epoxy Phenol Alumina 7-50 Granular Epoxy Phenol Organic 7-50

As illustrated in FIG. 7, the conductive layer 441 and the substrate orcarrier 442 can be removed by any suitable technique or process, such asby peeling and/or etching, which can result in a finished bridge 430. Inone embodiment mentioned above, the carrier 442 may comprise a peelablecore, which can be peeled at the peelable interface of the peelable coreto remove the carrier 442, followed by a copper etch to remove theconductive layer 441. Desired surface finish on the pads may then beperformed, followed by applying solder bumps (not shown) to finish thebridge. If desired, multiple bridges can be manufactured simultaneouslyby the processes disclosed herein. If needed, multiple bridges formedtogether can be singulated to form individual bridges. Any suitabletechnique, including mechanical and chemical techniques, can be utilizedto singulate (e.g., divide or separate) bridges from one another, suchas cutting (e.g., laser), sawing, shearing, milling, broaching, etching,etc.

In some cases, it may be desirable to have an encapsulant materialdisposed about at least a portion of the bridge 430, such as aboutportions of the routing layers. FIGS. 8A-8C illustrate a process foraccomplishing this. For example, FIG. 8A illustrates a plurality ofbridges 430 a-c, which are similar to the bridge 430 of FIG. 7, disposed(e.g., “pick and placed”) on a carrier 470. The carrier 470 can be ofany suitable configuration and made of any suitable type of material(e.g., stainless steel). A release material 471 (e.g., a thermal releasetape) can be disposed on the carrier 470 to facilitate release andseparation of finished bridges from the carrier. As illustrated in FIG.8B, encapsulant material 433 can be disposed over the bridges 430 a-c,such as by over-molding. Finished bridges 430 a′-c′, each with anencapsulant material 433 a′-c′, respectively, can be singulated andremoved from the carrier, as illustrated in FIG. 8C. The presentdisclosure therefore provides a bridge that can be manufactured usinglow-cost substrate packaging (e.g., molding) instead of typicalexpensive wafer fabrication processes.

Finished bridges can be disposed (e.g., “pick and placed”) in desiredpackage substrate locations for providing electrical interconnectsbetween electronic components. Once disposed in, or combined with, apackage substrate, typical processing can be utilized to prepare thepackage substrate for coupling with electronic components.

FIG. 9 illustrates an example computing system 502. The computing system502 can include an electronic device package 500 as disclosed herein,coupled to a motherboard 580. In one aspect, the computing system 502can also include a processor 581, a memory device 582, a radio 583, aheat sink 584, a port 585, a slot, or any other suitable device orcomponent, which can be operably coupled to the motherboard 580. Thecomputing system 502 can comprise any type of computing system, such asa desktop computer, a laptop computer, a tablet computer, a smartphone,a server, etc. Other embodiments need not include all of the featuresspecified in FIG. 9, and may include alternative features not specifiedin FIG. 9.

EXAMPLES

The following examples pertain to further embodiments.

In one example there is provided an electrical interconnect bridgecomprising a bridge substrate formed of a mold compound material, aplurality of routing layers within the bridge substrate, each routinglayer having a plurality of FLS traces, and a via extending through thesubstrate and electrically coupling at least one of the FLS traces inone of the routing layers to at least one of the FLS traces in anotherof the routing layers.

In one example of an electrical interconnect bridge, the bridgesubstrate mold compound material of a first routing layer of theplurality of routing layers includes a first mold compound material andthe bridge substrate mold compound material of a second routing layer ofthe plurality of routing layers includes a second mold compoundmaterial.

In one example of an electrical interconnect bridge, the bridgesubstrate of the plurality of routing layers includes the same moldcompound material.

In one example of an electrical interconnect bridge, the mold compoundmaterial comprises epoxy phenol, epoxy anhydride, epoxy amine, or acombination thereof.

In one example of an electrical interconnect bridge, the first andsecond plurality of FLS traces have a maximum width of about 10 μm.

In one example of an electrical interconnect bridge, the first pluralityof FLS traces are spaced from one another by at most about 10 μm.

In one example of an electrical interconnect bridge, the secondplurality of FLS traces are spaced from one another by at most about 10μm.

In one example of an electrical interconnect bridge, the via has anon-circular cross-section.

In one example of an electrical interconnect bridge, the bridgesubstrate further comprises an encapsulant material disposed at leastpartially about each of the plurality of routing layers.

In one example of an electrical interconnect bridge, a CTE of the moldcompound material is from about 7 to about 25 ppm per degree Celsius.

In one example there is provided an electrical interconnect bridgeprecursor comprising a trace having a via pad, and a spacer formed of asacrificial material disposed on the via pad.

In one example of an electrical interconnect bridge precursor, the tracehas a maximum width of about 10 μm.

In one example of an electrical interconnect bridge precursor, the tracecomprises a plurality of traces that are spaced from one another by atmost about 10 μm.

In one example of an electrical interconnect bridge precursor, thesacrificial material is thermally decomposable.

In one example of an electrical interconnect bridge precursor, thesacrificial material comprises polynorbornene, polycarbonate, or acombination thereof.

In one example of an electrical interconnect bridge precursor, thespacer has a non-circular cross-section.

In one example of an electrical interconnect bridge precursor, theelectrical interconnect bridge precursor comprises mold compoundmaterial disposed at least partially about lateral sides of the spacer,the sacrificial material facilitating removal of the spacer such that anopening remains in the mold compound material in communication with thevia pad.

In one example of an electrical interconnect bridge precursor, theelectrical interconnect bridge precursor comprises a carrier supportingthe trace.

In one example there is provided an electronic device package substrateassembly comprising a package substrate, and an electrical interconnectbridge embedded in the package substrate configured to route electricalsignals between a first electronic component and a second electroniccomponent coupled to the package substrate, the electrical interconnectbridge having a bridge substrate formed of a mold compound material, afirst routing layer within the bridge substrate having a first pluralityof FLS traces, a second routing layer disposed proximate the firstrouting layer within the bridge substrate having a second plurality ofFLS traces, and a via extending through the bridge substrate andelectrically coupling at least one of the first plurality of FLS tracesto at least one of the second plurality of FLS traces.

In one example of an electronic device package substrate assembly, thebridge substrate mold compound material of the first routing layerincludes a first mold compound material and the bridge substrate moldcompound material of the second routing layer includes a second moldcompound material.

In one example of an electronic device package substrate assembly, thebridge substrate of the first and second routing layers includes thesame mold compound material.

In one example of an electronic device package substrate assembly, themold compound material comprises epoxy phenol, epoxy anhydride, epoxyamine, or a combination thereof.

In one example of an electronic device package substrate assembly, thefirst and second plurality of FLS traces have a maximum width of about10 μm.

In one example of an electronic device package substrate assembly, thefirst plurality of FLS traces are spaced from one another by at mostabout 10 μm.

In one example of an electronic device package substrate assembly, thesecond plurality of FLS traces are spaced from one another by at mostabout 10 μm.

In one example of an electronic device package substrate assembly, thevia has a non-circular cross-section.

In one example of an electronic device package substrate assembly, thebridge substrate further comprises an encapsulant material disposed atleast partially about the first and second routing layers, such that theencapsulant material is proximate a portion of the package substrate.

In one example of an electronic device package substrate assembly, a CTEof the mold compound material is from about 7 to about 25 ppm per degreeCelsius.

In one example there is provided an electronic device package comprisinga first electronic component, a second electronic component, a packagesubstrate, and an electrical interconnect bridge embedded in the packagesubstrate to route electrical signals between the first electroniccomponent and the second electronic component, the electricalinterconnect bridge having a bridge substrate formed of a mold compoundmaterial, a first routing layer within the bridge substrate having afirst plurality of FLS traces, a second routing layer disposed proximatethe first routing layer within the bridge substrate having a secondplurality of FLS traces, and a via extending through the bridgesubstrate and electrically coupling at least one of the first pluralityof FLS traces to at least one of the second plurality of FLS traces.

In one example of an electronic device package, the bridge substratemold compound material of the first routing layer includes a first moldcompound material and the bridge substrate mold compound material of thesecond routing layer includes a second mold compound material.

In one example of an electronic device package, the bridge substrate ofthe first and second routing layers includes the same mold compoundmaterial.

In one example of an electronic device package, the mold compoundmaterial comprises epoxy phenol, epoxy anhydride, epoxy amine, or acombination thereof.

In one example of an electronic device package, the first and secondplurality of FLS traces have a maximum width of about 10 μm.

In one example of an electronic device package, the first plurality ofFLS traces are spaced from one another by at most about 10 μm.

In one example of an electronic device package, the second plurality ofFLS traces are spaced from one another by at most about 10 μm.

In one example of an electronic device package, the via has anon-circular cross-section.

In one example of an electronic device package, the bridge substratefurther comprises an encapsulant material disposed at least partiallyabout the first and second routing layers, such that the encapsulantmaterial is proximate a portion of the package substrate.

In one example of an electronic device package, a CTE of the moldcompound material is from about 7 to about 25 ppm per degree Celsius.

In one example there is provided a computing system comprising amotherboard, and an electronic device package operably coupled to themotherboard, the electronic device package including a first electroniccomponent, a second electronic component, a package substrate, and anelectrical interconnect bridge embedded in the package substrate toroute electrical signals between the first electronic component and thesecond electronic component, the electrical interconnect bridge having abridge substrate formed of a mold compound material, a first routinglayer within the bridge substrate having a first plurality of FLStraces, a second routing layer disposed proximate the first routinglayer within the bridge substrate having a second plurality of FLStraces, and a via extending through the bridge substrate andelectrically coupling at least one of the first plurality of FLS tracesto at least one of the second plurality of FLS traces.

In one example of a computing system, the computing system comprises adesktop computer, a laptop, a tablet, a smartphone, a server, or acombination thereof.

In one example of a computing system, the computing system furthercomprises a processor, a memory device, a heat sink, a radio, a slot, aport, or a combination thereof operably coupled to the motherboard.

In one example there is provided a method for making a via forelectrically coupling conductive elements comprising forming a spacer ona conductive element, molding a mold material at least partially aboutlateral sides of the spacer, removing the spacer to form an opening inthe mold material in communication with the conductive element, anddisposing a conductive material in the opening to form a via.

In one example of a method for making a via for electrically couplingconductive elements, forming a spacer comprises disposing a sacrificialmaterial on the conductive element.

In one example of a method for making a via for electrically couplingconductive elements, the conductive element comprises a via pad.

In one example of a method for making a via for electrically couplingconductive elements, disposing a sacrificial material on the conductiveelement comprises curtain coating, spin coating, printing, dispensing,or a combination thereof.

In one example of a method for making a via for electrically couplingconductive elements, the method comprises defining a shape of thespacer.

In one example of a method for making a via for electrically couplingconductive elements, defining a shape of the spacer comprisesphoto-defining the shape, dry etching the shape, or a combinationthereof.

In one example of a method for making a via for electrically couplingconductive elements, the shape of the spacer has a non-circularcross-section.

In one example of a method for making a via for electrically couplingconductive elements, molding a mold material about the spacer comprisescompression molding such that the spacer is flush with the moldmaterial.

In one example of a method for making a via for electrically couplingconductive elements, the spacer is formed of a sacrificial material, andwherein removing the spacer comprises heating the spacer sufficient todecompose the sacrificial material.

In one example of a method for making a via for electrically couplingconductive elements, the sacrificial material comprises polynorbornene,polycarbonate, or a combination thereof.

In one example of a method for making a via for electrically couplingconductive elements, disposing a conductive material in the openingcomprises forming a seed layer of the conductive material, plating theconductive material, or a combination thereof.

In one example of a method for making a via for electrically couplingconductive elements, the conductive element comprises at least one of atrace and a via pad.

In one example of a method for making a via for electrically couplingconductive elements, the trace has a maximum width of about 10 μm.

In one example of a method for making a via for electrically couplingconductive elements, the trace comprises a plurality of traces that arespaced from one another by at most about 10 μm.

In one example of a method for making a via for electrically couplingconductive elements, the method comprises disposing conductive materialon the via to form a second conductive element.

In one example of a method for making a via for electrically couplingconductive elements, the method comprises forming a second spacer on thesecond conductive element, molding a mold material at least partiallyabout lateral sides of the second spacer, removing the second spacer toform a second opening in the mold material in communication with thesecond conductive element, and disposing a conductive material in thesecond opening to form a second via.

In one example of a method for making a via for electrically couplingconductive elements, the second conductive element comprises a trace.

In one example of a method for making a via for electrically couplingconductive elements, the trace has a maximum width of about 10 μm.

In one example of a method for making a via for electrically couplingconductive elements, the trace comprises a plurality of traces that arespaced from one another by at most about 10 μm.

In one example there is provided a method for making an electricalinterconnect bridge comprising forming a first conductive element,forming a via as described herein on the first conductive element, andforming a second conductive element on the via.

In one example there is provided an electrical interconnect bridge madeby the above method.

Circuitry used in electronic components or devices (e.g. a die) of anelectronic device package can include hardware, firmware, program code,executable code, computer instructions, and/or software. Electroniccomponents and devices can include a non-transitory computer readablestorage medium which can be a computer readable storage medium that doesnot include signal. In the case of program code execution onprogrammable computers, the computing devices recited herein may includea processor, a storage medium readable by the processor (includingvolatile and non-volatile memory and/or storage elements), at least oneinput device, and at least one output device. Volatile and non-volatilememory and/or storage elements may be a RAM, EPROM, flash drive, opticaldrive, magnetic hard drive, solid state drive, or other medium forstoring electronic data. Node and wireless devices may also include atransceiver module, a counter module, a processing module, and/or aclock module or timer module. One or more programs that may implement orutilize any techniques described herein may use an applicationprogramming interface (API), reusable controls, and the like. Suchprograms may be implemented in a high level procedural or objectoriented programming language to communicate with a computer system.However, the program(s) may be implemented in assembly or machinelanguage, if desired. In any case, the language may be a compiled orinterpreted language, and combined with hardware implementations.

While the forgoing examples are illustrative of the specific embodimentsin one or more particular applications, it will be apparent to those ofordinary skill in the art that numerous modifications in form, usage anddetails of implementation can be made without departing from theprinciples and concepts articulated herein.

1. An electrical interconnect bridge to be embedded in a packagesubstrate, comprising: a molded bridge substrate comprising a moldcompound material; a plurality of routing layers within the bridgesubstrate, each routing layer having a plurality of fine line and spaced(FLS) traces; and a via extending through the bridge substrate andelectrically coupling at least one of the FLS traces in one of therouting layers to at least one of the FLS traces in another of therouting layers to route electrical signals between a first electroniccomponent and a second electronic component supported by the packagesubstrate.
 2. The electrical interconnect bridge of claim 1, wherein afirst routing layer of the plurality of routing layers includes a firstmold compound material and a second routing layer of the plurality ofrouting layers includes a second mold compound material.
 3. Theelectrical interconnect bridge of claim 1, wherein the plurality ofrouting layers each includes the same mold compound material.
 4. Theelectrical interconnect bridge of claim 1, wherein the mold compoundmaterial comprises epoxy phenol, epoxy anhydride, epoxy amine, or acombination thereof.
 5. The electrical interconnect bridge of claim 1,wherein the first and second plurality of FLS traces have a maximumwidth of about 10 μm.
 6. The electrical interconnect bridge of claim 1,wherein the first plurality of FLS traces are spaced from one another byno more than about 10 μm.
 7. The electrical interconnect bridge of claim6, wherein the second plurality of FLS traces are spaced from oneanother by no more than about 10 μm.
 8. The electrical interconnectbridge of claim 1, wherein the via has a non-circular cross-section. 9.The electrical interconnect bridge of claim 1, wherein the bridgesubstrate further comprises an encapsulant material disposed at leastpartially about each of the plurality of routing layers.
 10. Theelectrical interconnect bridge of claim 1, wherein a CTE of the moldcompound material is from about 7 to about 25 ppm per degree Celsius.11. An electronic device package substrate assembly, comprising: apackage substrate; and an electrical interconnect bridge embedded in thepackage substrate configured to route electrical signals between a firstelectronic component and a second electronic component coupled to thepackage substrate, the electrical interconnect bridge having a moldedbridge substrate comprising a mold compound material, a first routinglayer within the bridge substrate having a first plurality of fine lineand spaced (FLS) traces, a second routing layer disposed proximate thefirst routing layer within the bridge substrate having a secondplurality of FLS traces, and a via extending through the bridgesubstrate and electrically coupling at least one of the first pluralityof FLS traces to at least one of the second plurality of FLS traces. 12.The electronic device package substrate assembly of claim 11, whereinthe first routing layer includes a first mold compound material and thesecond routing layer includes a second mold compound material.
 13. Theelectronic device package substrate assembly of claim 11, wherein thefirst and second routing layers include the same mold compound material.14. The electronic device package substrate assembly of claim 11,wherein the mold compound material comprises epoxy phenol, epoxyanhydride, epoxy amine, or a combination thereof.
 15. The electronicdevice package substrate assembly of claim 11, wherein the first andsecond plurality of FLS traces have a maximum width of about 10 μm. 16.The electronic device package substrate assembly of claim 11, whereinthe first plurality of FLS traces are spaced from one another by no morethan about 10 μm.
 17. The electronic device package substrate assemblyof claim 16, wherein the second plurality of FLS traces are spaced fromone another by no more than about 10 μm.
 18. The electronic devicepackage substrate assembly of claim 11, wherein the via has anon-circular cross-section.
 19. The electronic device package substrateassembly of claim 11, wherein the bridge substrate further comprises anencapsulant material disposed at least partially about the first andsecond routing layers, such that the encapsulant material is proximate aportion of the package substrate.
 20. The electronic device packagesubstrate assembly of claim 11, wherein a CTE of the mold compoundmaterial is from about 7 to about 25 ppm per degree Celsius.
 21. Amethod for making a via for electrically coupling conductive elements,comprising: forming a spacer on a conductive element; molding a moldmaterial at least partially about lateral sides of the spacer; removingthe spacer to form an opening in the mold material in communication withthe conductive element; and disposing a conductive material in theopening to form a via.
 22. The method of claim 21, wherein forming aspacer comprises disposing a sacrificial material on the conductiveelement.
 23. The method of claim 21, further comprising defining a shapeof the spacer.
 24. The method of claim 21, wherein molding a moldmaterial about the spacer comprises compression molding such that thespacer is flush with the mold material.
 25. The method of claim 21,wherein the spacer is formed of a sacrificial material, and whereinremoving the spacer comprises heating the spacer sufficient to decomposethe sacrificial material.
 26. The method of claim 21, wherein disposinga conductive material in the opening comprises forming a seed layer ofthe conductive material, plating the conductive material, or acombination thereof.
 27. The method of claim 21, wherein the conductiveelement comprises at least one of a trace and a via pad.
 28. The methodof claim 21, further comprising disposing conductive material on the viato form a second conductive element.